Conference MC&FPGA

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FPGA Implementation of Floating-Point Significand Multiplier

DOI: 10.35598/mcfpga.2021.004

FPGA Implementation of Floating-Point Significand Multiplier
Artem Didenko, Irina Zeleneva

III International Scientific and Practical Conference Theoretical and Applied Aspects of Device Development on Microcontrollers and FPGAs (MC&FPGA), Kharkiv, Ukraine, 2021, pp. 13-14.

Abstract
Development of high-performance computational devices needs fast methods of operations with numbers which are presented in floating-point format. One of the most common approaches to build a significand multiplier is using a Wallace CSA-adder tree structure which shows good performance in adding partial sums. Significand multiplier was implemented in FPGA as a part of floating-point multiplier which works with single precision numbers in IEEE-754 standard.

Keywords: multiplier, floating-point number, carry-save adder, FPGA.

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