Conference MC&FPGA

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Miniaturization of Control Devices on Programmable Logic Chips

DOI: 10.35598/mcfpga.2022.003

Miniaturization of Control Devices on Programmable Logic Chips
Svitlana Hrushko, Irina Zeleneva, Artur Timenko, Nataliia Kulykovska

IV International Scientific and Practical Conference Theoretical and Applied Aspects of Device Development on Microcontrollers and FPGAs (MC&FPGA-2022), Kharkiv, Ukraine, 2022, pp. 11-12.

Date of Conference: 2324 June 2022

Abstract
The paper is devoted to solving the topical scientific problem of developing the structures and methods for synthesis of the combined finite state  machines (CFSM), aimed at reducing equipment costs when implementing the CFSM logical scheme in the basis of programmable logic integrated circuits  such as FPGA and CPLD.

Keywords: combined FSM, FPGA, CPLD, logic circuit, embedded memory, pseudo-equivalent states.

Full Text:   PDF

References

  1. Intel documentation. Available: www.intel.com/content/www/us/ en/products/programmable.html
  2. Xilinx documentation. Available: from www. www.xilinx.com/
  3. Microsemi documentation. Available: https://www.microsemi.com/ product-directory/ 1636-fpga-soc
  4. U. Farooq, Tree-based Heterogeneous FPGA Architectures: Application Specific Exploration and Optimization. Berlin: Springer, 2012.
  5. S.S. Hrushko, “Implementing combined FSM with heterogeneous FPGA”, presented at the Conf. Proc. of 14th Int. Conf. on Advanced Trends in Radioelectronics, Telecomm. and Comp. Eng. (TCSET), Lviv-Slavske, Ukraine, Feb. 2018.
  6. A. A. Barkalov, L. A. Titarenko, I. Y. Zeleneva and S. S. Hrushko, “Ispol’zovanie psevdojekvivalentnyh sostojanij v sovmeshhennom mikroprogrammnom avtomate” [Using pseudoequivalent states in a combined finite state mashine]”, Naukovi praci Donecz`kogo nacional`nogo texnichnogo universy`tetu. Seriya : Informaty`ka, kibernety`ka ta obchy`slyuval`na texnika, no. 1, pp. 5–11 2017.  (in Russian).
  7. A. Barkalov, L. Titarenko, I. Zeleneva and S. Hrushko “Implementing combined FSM with CPLDs”, International Journal of Software Eng. and Com. Sys. (IJSECS), vol. 4, no. 1, pp. 75-83, 2017.