Testability Increasing Method by Introducing Hardware Redundancy in the Easy-tested Finite State Machines

DOI: 10.35598/mcfpga.2019.002

Testability Increasing Method by Introducing Hardware Redundancy in the Easy-tested Finite State Machines
Marina Miroshnyk, Pavlo Galkin, Olga Zaichenko, Roman Tsekhmistro

Theoretical and Applied Aspects of Device Development on Microcontrollers and FPGAs, MC&FPGA. – 2019. – P. 9-11.

Abstract
Testability increasing methods by introducing hardware redundancy into the circuit implementation are sufficiently developed and widely used in the design. Since the construction of the testing sequence is based on the use of automaton diagrams, it eliminates the need to analyze the circuit implementation of the remote control when building a diagnostic experiment. This approach allows us to extend the class of detectable faults, which in structural-analytical test generation methods is limited, as a rule, to a multitude of single constant faults. The use of automaton models in the construction of tests allows to detect any malfunction that changes the automaton diagram of a serviceable remote control and does not increase the number of states of remote control memory elements. There was described finite state machine using hardware description language. The method of computer-aided design of the easytested control FSM by introducing the hardware redundancy is presented in the paper. The FSM model is represented in VHDL in the form of the FSM template. The solution way is to add additional fragments of the VHDL code, which ensure the forced setting of the FSM into an arbitrary state without the use of synchronizing sequences. The use of the shift register in the memory part of the control FSM for organizing the path scanning was considered. The method of FSM state table expansion, which ensures the mode of bypassing all nodes of the FSM’ state diagram in the diagnostic mode was proposed.

Keywords:  easy tested finite state machine, Hamiltonian cycle, distinguishing sequence, homing sequence, shift register

Full Text:   PDF

References

1. P. Bibilo and V. Romanov, “Construction of compact tests for functional verification of VHDL descriptions of finite automata”,Control systems and machines, №1, 2017, pp.35-45.
2. V. Semenets, G. Krivulya, A. Gorbatyuk, and A. Shilverst, VHDL for designing computer devices. Kharkov: Publishing House of Kharkov Technical University of Radio electronics, 2001,p.164.
3. P. Bibilo Synthesis of logic circuits using the VHDL language. M: SOLON-P, 2009, p.384.
4. A. Dolmatov and A. Petrov,  XILINX XST synthesis technology. Laboratory work 3. Ekaterinburg: Publishing House of Ural State Technical University, 2005, p.23.
5. ISE. In-Depth Tutorial, UG695 (v14.1). 2012. Xilinx, p.150.
6. P. Parkhomenko and E. Soghomonyan,Basics of technical diagnostics. M: Energy, 1981, p.320.
7. F. Hennine, “Fault detecting experiments for sequential circuits,” 5th Annual Symposium on Switching Circuit Theory and Logical Design, 1964, pp.95-100. doi:10.1109/SWCT.1964.8.
8. V. Totsenko, Algorithms for technical diagnostics of discrete devices. M: Radio and communication, 1983, p.240.
9. M. Miroschnyk, T. Korytchinko, O. Demihev, V. Krylova, D. Karaman and I. Filippenko, “Practical methods for de Bruijn sequences generation using non-linear feedback shift registers,” 2018 14th International Conference on Advanced Trends in Radioelecrtronics, Telecommunications and Computer Engineering (TCSET), Slavske, 2018, pp. 1157-1161. doi: 10.1109/TCSET.2018.8336400.
10. M. Miroshnyk, Y. Pakhomov, E. German, A. Shkil, E. Kulak and D. Kucherenko, “Design automation of testable finite state machines,” 2017 15th IEEE East-West Design and Test Symposium (EWDTS), Novi Sad, 2017, pp.1-6. doi: 10.1109/EWDTS.2017.8110034.
11. M. Miroshnyk, S. Poroshin, A. Shkil, E. Kulak, I. Filippenko and D. Kucherenko, “Design logical control units with finite state machine patterns,”.2018 16th IEEE East-West Design and Test Symposium (EWDTS), Kazan, 2018, pp.203-208. doi: 10.1109/EWDTS.2018.8524869.
12. O. Drozd, M. Kuznietsov, O. Martynyuk and M. Drozd, “A method of the hidden faults elimination in FPGA projets for the critical applications,” 2018 IEEE 9th International Conference on Dependable Systems, Services and Technologies (DESSERT), 2018, Kiev, pp. 218-221. doi:10.1109/DESSERT.2018.8409131.
13. G. Kuchuk, V. Kharchenko, A. Kovalenko and E. Ruchkov,  “Approaches to selection of combinatorial algorithm for optimization in network traffic control of safety-critical systems,” 2016 IEEE East-West Design and Test Symposium (EWDTS),  2016, Yerevan, pp. 1-6.  doi: 10.1109/EWDTS.2016.7807655.
14. I. Furman, M. Malinovsky, S. Bovchaliuk, А. Allashev, “Retrospective analysis of the development of a parallel-action PLC architecture,” Bulletin of Kharkiv National Technical University for Petro Vasylenka, 2016, №176, pp.35-38.