Testability Increasing Method by Introducing Hardware Redundancy in the Easy-tested Finite State Machines
Marina Miroshnyk, Pavlo Galkin, Olga Zaichenko, Roman Tsekhmistro
Theoretical and Applied Aspects of Device Development on Microcontrollers and FPGAs, MC&FPGA. – 2019. – P. 9-11.
Testability increasing methods by introducing hardware redundancy into the circuit implementation are sufficiently developed and widely used in the design. Since the construction of the testing sequence is based on the use of automaton diagrams, it eliminates the need to analyze the circuit implementation of the remote control when building a diagnostic experiment. This approach allows us to extend the class of detectable faults, which in structural-analytical test generation methods is limited, as a rule, to a multitude of single constant faults. The use of automaton models in the construction of tests allows to detect any malfunction that changes the automaton diagram of a serviceable remote control and does not increase the number of states of remote control memory elements. There was described finite state machine using hardware description language. The method of computer-aided design of the easytested control FSM by introducing the hardware redundancy is presented in the paper. The FSM model is represented in VHDL in the form of the FSM template. The solution way is to add additional fragments of the VHDL code, which ensure the forced setting of the FSM into an arbitrary state without the use of synchronizing sequences. The use of the shift register in the memory part of the control FSM for organizing the path scanning was considered. The method of FSM state table expansion, which ensures the mode of bypassing all nodes of the FSM’ state diagram in the diagnostic mode was proposed.
Keywords: easy tested finite state machine, Hamiltonian cycle, distinguishing sequence, homing sequence, shift register
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