ХНУРЕ Харківський національний університет радіоелектроніки

Конференція MC&FPGA

Мова:

Design and Synthesis of Multi-Bit Binary Adders on FPGA

DOI: 10.35598/mcfpga.2023.010

Design and Synthesis of Multi-Bit Binary Adders on FPGA
Volodymyr Hryha, Volodymyr Mandzyuk, Ihor Kohut, Andriy Pavlyshyn

V International Scientific and Practical Conference Theoretical and Applied Aspects of Device Development on Microcontrollers and FPGAs (MC&FPGA-2023), Kharkiv, Ukraine, 2023, pp. 32-35.

Date of Conference: 22–23 June 2023

Abstract
Fields of application and main classes of multi-bit binary adders (MBAs) are outlined. The well-known structures of cascade, parallel-serial and pyramidal multi-bit adders are analyzed and their system characteristics are determined when classical single-bit components are used. A comparison of the system characteristics of the MBA using the new single-bit components of full and partial adders is carried out. MBA structures were developed using hardware description languages, and their simulation and synthesis on FPGA was performed.

Keywords: adder, FPGA, algorithm, structure, hardware complexity, time complexity.

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